View EDS1616AGTA-75-E_2233708.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

document no. e0504e40 (ver. 4.0) date published june 2005 (k) japan printed in japan url: http://www.elpida.com ? elpida memory, inc. 2004-2005 data sheet 16m bits sdram eds1616agta (1m words 16 bits) description the eds1616agta is 16m bits sdram organized as 524,288 words 16 bits 2 banks. all inputs and outputs are synchronized with the positive edge of the clock. it is packaged in 50-pin plastic tsop (ii). features ? 3.3v power supply ? clock frequency: 166mhz/133mhz (max.) ? single pulsed /ras ? 16 organization ? 2 banks can operate simultaneously and independently ? burst read/write operation and burst read/single write operation capability ? programmable burst length (b l): 1, 2, 4, 8 and full page ? 2 variations of burst sequence ? sequential (bl = 1, 2, 4, 8, full page) ? interleave (bl = 1, 2, 4, 8) ? programmable /cas latency (cl): 2, 3 ? byte control by udqm and ldqm ? refresh cycles: 2048 refresh cycles/32ms ? 2 variations of refresh ? auto refresh ? self refresh ? tsop (ii) package with lead free solder (sn-bi) pin configurations /xxx indicate active low signal. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 vss dq15 dq14 vssq dq13 dq12 vddq dq11 dq10 vssq dq9 dq8 vddq nc udqm clk cke nc a9 a8 a7 a6 a5 a4 vss vdd dq0 dq1 vssq dq2 dq3 vddq dq4 dq5 vssq dq6 dq7 vddq ldqm /we /cas /ras /cs ba a10 a0 a1 a2 a3 vdd 50-pin plastic tsop (ii) (top view) address input bank select address data-input/output chip select row address strobe column address strobe write enable a0 to a10 ba dq0 to dq15 /cs /ras /cas /we input/output mask clock enable clock input power for internal circuit ground for internal circuit power for dq circuit ground for dq circuit no connection ldqm, udqm cke clk vdd vss vddq vssq nc
eds1616agta data sheet e0504e40 (ver. 4.0) 2 ordering information part number supply voltage organization (words bits) internal banks clock frequency mhz (max.) /cas latency package eds1616agta-6b-e 3.3v 1m 16 2 166 100 3 2 50-pin plastic tsop (ii) EDS1616AGTA-75-E 133 100 3 2 part number environment code e: lead free elpida memory density / bank 16: 16m/2-bank organization 16: x16 power supply, interface a: 3.3v, lvttl die rev. package ta: tsop (ii) speed 6b: 166mhz/cl3 100mhz/cl2 75: 133mhz/cl3 100mhz/cl2 product family s: sdram type d: monolithic device

eds1616agta data sheet e0504e40 (ver. 4.0) 3 contents description.................................................................................................................... .................................1 features....................................................................................................................... ..................................1 pin config urations ............................................................................................................. ............................1 ordering in format ion........................................................................................................... ...........................2 part nu mber .................................................................................................................... ..............................2 electrical sp ecifications...................................................................................................... ...........................4 block diagram .................................................................................................................. ...........................10 pin function................................................................................................................... ..............................11 command oper ation .............................................................................................................. .....................12 simplified st ate di agram ....................................................................................................... ......................20 mode register co nfiguration.................................................................................................... ...................21 power-up sequen ce.............................................................................................................. .......................23 operation of the s dram......................................................................................................... ....................24 timing wave forms............................................................................................................... ........................40 package dr awing ................................................................................................................ ........................46 recommended solder ing conditions............................................................................................... ...........47
eds1616agta data sheet e0504e40 (ver. 4.0) 4 electrical specifications ? all voltages are referenced to vss (gnd). ? after power up, execute power up sequence and initializatio n sequence before proper device operation is achieved (refer to the power up sequence). absolute maximum ratings parameter symbol rating unit note voltage on any pin relative to vss vt ?0.5 to vdd + 0.5 ( 4.6 (max.)) v supply voltage relative to vss vdd ?0.5 to +4.6 v short circuit output current ios 50 ma power dissipation pd 1.0 w operating ambient temperature ta 0 to +70 c storage temperature tstg ?55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this speci fication. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (ta = 0 c to +70 c) parameter symbol min. max. unit notes supply voltage vdd, vddq 3.0 3.6 v 1 vss, vssq 0 0 v 2 input high voltage vih 2.0 vdd + 0.3 v 3 input low voltage vil ?0.3 0.8 v 4 notes: 1. the supply voltage with all vdd and vddq pins must be on the same level. 2. the supply voltage with all vss and vssq pins must be on the same level. 3. vih (max.) = vdd + 1.5v (pulse width 5ns). 4. vil (min.) = vss ? 1.5v (pulse width 5ns).
eds1616agta data sheet e0504e40 (ver. 4.0) 5 dc characteristics 1 (ta = 0 c to +70 c, vdd, vddq = 3.3v 0.3v, vss, vssq = 0v) parameter symbol grade max. unit test condition notes operating current idd1 -6b -75 100 90 ma burst length = 1 trc = trc (min.) 1, 2, 3 standby current in power down idd2p 1 ma cke = vil, tck = tck (min.) 6 standby current in power down (input signal stable) idd2ps 1 ma cke = vil, tck = 7 standby current in non power down idd2n 15 ma cke, /cs = vih, tck = tck (min.) 4 standby current in non power down (input signal stable) idd2ns 5 ma cke = vih, tck = , /cs = vih 8 active standby current in power down idd3p 4 ma cke = vil, tck = tck (min.) 1, 2, 6 active standby current in power down (input signal stable) idd3ps 4 ma cke = vil, tck = 2, 7 active standby current in non power down idd3n 25 ma cke, /cs = vih, tck = tck (min.) 1, 2, 4 active standby current in non power down (input signal stable) idd3ns 15 ma cke = vih, tck = , /cs = vih 2, 8 burst operating current idd4 -6b -75 120 110 ma tck = tck (min.), bl = 4 1, 2, 5 refresh current idd5 -6b -75 100 90 ma trc = trc (min.) 3 self refresh current idd6 1 ma vih vdd ? 0.2v vil 0.2v notes: 1. idd depends on output load c ondition when the device is selected. idd (max.) is specif ied at the output open condition. 2. one bank operation. 3. input signals are changed once per one clock. 4. input signals are changed once per two clocks. 5. input signals are chan ged once per four clocks. 6. after power down mode, clk operating current. 7. after power down mode, no clk operating current. 8. input signals ar e vih or vil fixed.
eds1616agta data sheet e0504e40 (ver. 4.0) 6 dc characteristics 2 (ta = 0 c to +70 c, vdd, vddq = 3.3v 0.3v, vss, vssq = 0v) parameter symbol min. max. unit test condition notes input leakage current ili ?1 1 a 0 vin vdd output leakage current ilo ?1.5 1.5 a 0 vout vdd, dq = disable output high voltage voh 2.4 ? v ioh = ?2 ma output low voltage vol ? 0.4 v iol = 2 ma pin capacitance (ta = 25c, vdd, vddq = 3.3v 0.3v) parameter symbol pins min. typ. max. unit notes input capacitance ci1 clk 2.5 ? 4.0 pf 1, 2, 4 ci2 address, cke, /cs, /ras, /cas, /we, dqm 2.5 ? 5.0 pf 1, 2, 4 data input/output capacitance ci/o dq 4.0 ? 6.5 pf 1, 2, 3, 4 notes: 1. capacitance measured with boonton me ter or effective capacitance measuring method. 2. measurement condition: f = 1mhz, 1.4v bias, 200mv swing. 3. dqm = vih to disable dout. 4. this parameter is sampled and not 100% tested.
eds1616agta data sheet e0504e40 (ver. 4.0) 7 ac characteristics (ta = 0 c to +70 c, vdd, vddq = 3.3v 0.3v, vss, vssq = 0v) -6b -75 parameter symbol min. max. min. max. unit notes system clock cycle time (cl = 2) tck 10 ? 10 ? ns 1 (cl = 3) tck 6 ? 7.5 ? ns 1 clk high pulse width tch 2.5 ? 2.5 ? ns 1 clk low pulse width tcl 2.5 ? 2.5 ? ns 1 access time from clk tac ? 5.4 ? 5.4 ns 1, 2 data-out hold time toh 2 ? 2 ? ns 1, 2 clk to data-out low impedance tlz 0 ? 0 ? ns 1, 2, 3 clk to data-out high impedance thz ? 5.4 ? 5.4 ns 1, 4 input setup time tsi 1.5 ? 1.5 ? ns 1 input hold time thi 0.8 ? 0.8 ? ns 1 ref/active to ref/active command period trc 60 ? 67.5 ? ns 1 active to precharge command period tras 42 120000 45 120000 ns 1 active command to column command (same bank) trcd 18 ? 20 ? ns 1 precharge to active command period trp 18 ? 20 ? ns 1 write recovery or data-in to precharge lead time tdpl 12 ? 15 ? ns 1 last data into active latency tdal 2clk + 18ns ? 2clk + 20ns ? active (a) to active (b) command period trrd 12 ? 15 ? ns 1 transition time (rise and fall) tt 0.5 5 0.5 5 ns refresh period (2048 refresh cycles) tref ? 32 ? 32 ms notes: 1. ac measurement assumes tt = 0.5ns. re ference level for timing of input signals is 1.4v. 2. access time is measured at 1.4v. load condition is cl = 30pf. 3. tlz (min.) defines the time at which th e outputs achieves the low impedance state. 4. thz (max.) defines the time at which the outputs achieves the high impedance state.
eds1616agta data sheet e0504e40 (ver. 4.0) 8 test conditions ? ac high level voltage/low level input voltage: 2.4v/0.4v ? input and output timing reference levels: 1.4v ? input waveform and output load: see following figures tt 2.4 v 0.4 v 0.8 v 2.0 v input t t i/o cl input waveform and output load
eds1616agta data sheet e0504e40 (ver. 4.0) 9 relationship between frequency and minimum latency parameter -6b -75 frequency (mhz) 166 100 133 100 tck (ns) symbol 6 10 7.5 10 unit notes active command to column command (same bank) l rcd 3 2 3 2 tck 1 active command to active command (same bank) l rc 10 7 9 7 tck 1 active command to precharge command (same bank) l ras 7 5 6 5 tck 1 precharge command to active command (same bank) l rp 3 2 3 2 tck 1 write recovery or data-in to precharge command (same bank) l dpl 2 2 2 2 tck 1 active command to active command (different bank) l rrd 2 2 2 2 tck 1 self refresh exit time l srex 1 1 1 1 tck 2 last data in to active command (auto precharge, same bank) l dal 5 4 5 4 tck = [ l dpl + l rp] self refresh exit to command input l sec 10 7 9 7 tck = [ l rc] 3 precharge command to high impedance (cl = 2) l hzp ? 2 ? 2 tck (cl = 3) l hzp 3 3 3 3 tck last data out to active command (auto precharge, same bank) l apr 1 1 1 1 tck last data out to precharge (early precharge) (cl = 2) l ep ? ?1 ? ?1 tck (cl = 3) l ep ?2 ?2 ?2 ?2 tck column command to column command l ccd 1 1 1 1 tck write command to data in latency l wcd 0 0 0 0 tck dqm to data in l did 0 0 0 0 tck dqm to data out l dod 2 2 2 2 tck cke to clk disable l cle 1 1 1 1 tck register set to active command l mrd 2 2 2 2 tck /cs to command disable l cdd 0 0 0 0 tck power down exit to command input l pec 1 1 1 1 tck notes: 1. l rcd to l rrd are recommended value. 2. be valid [desl] or [nop] at next command of self refresh exit. 3. except [desl] and [nop]
eds1616agta data sheet e0504e40 (ver. 4.0) 10 block diagram clock generator mode register command decoder control logic row address buffer & refresh counter column address buffer & burst counter data control circuit latch circuit input & output buffer dq dqm clk cke address /cs /ras /cas /we bank 1 sense amplifier column decoder & latch circuit bank 0 row decoder
eds1616agta data sheet e0504e40 (ver. 4.0) 11 pin function clk (input pin) clk is the master clock input. other inputs signals are referenced to the clk rising edge. cke (input pins) cke determine validity of the next clk (clock). if cke is high, the next clk rising edge is valid; otherwise it is invalid. if the clk rising edge is invalid, the internal clock is not issued and the synchronous dram suspends operation. when the synchronous dram is not in burst mode and cke is negated, the device enters power down mode. during power down mode, cke must remain low. /cs (input pins) /cs low starts the command input cycle. when /cs is high, commands are ignored but operations continue. /ras, /cas, and /we (input pins) /ras, /cas and /we have the same symbols on conventional dra m but different functions. for details, refer to the command table. a0 to a10 (input pins) row address is determined by a0 to a10 at the clk (clock) rising edge in the active command cycle. column address is determined by a0 to a7 at the clk rising edge in the read or write command cycle. a10 defines the precharge mode. when a10 is high in t he precharge command cycle, all banks are precharged; when a10 is low, only the bank selected by ba is precharged. when a10 is high in read or write command cycle, the pr echarge starts automatically after the burst access. ba (input pin) ba is bank select signal (bs). (see bank select signal table) [bank select signal table] ba bank 0 l bank 1 h remark: h: vih. l: vil. udqm and ldqm (input pins) udqm and ldqm control input/output buffers. udqm and ldqm control upper byte (dq8 to dq15) and lower byte (dq0 to dq7). dq0 to dq15 (input/output pins) dq pins have the same function as i/o pins on a conventional dram. vdd, vss, vddq, vssq (power supply) vdd and vss are power supply pins for internal circuits . vddq and vssq are power supply pins for the output buffers.
eds1616agta data sheet e0504e40 (ver. 4.0) 12 command operation command truth table the sdram recognizes the following commands specif ied by the /cs, /ras, /cas, /we and address pins. cke function symbol n ? 1 n /cs /ras /cas /we ba a10 a0 to a9 device deselect desl h h no operation nop h l h h h burst stop bst h l h h l read read h l h l h v l v read with auto precharge reada h l h l h v h v write writ h l h l l v l v write with auto precharge writa h l h l l v h v bank activate act h l l h h v v v precharge select bank pre h l l h l v l precharge all banks pall h l l h l h mode register set mrs h l l l l l l v remark: h: vih. l: vil. : vih or vil. v: valid address input. device deselect command [desl] when this command is set (/cs is high), the sdram ignore command input at the clock. however, the internal status is held. no operation [nop] this command is not an execution command. however, the internal operations continue. burst stop command [bst] this command can stop the current burst operation. column address strobe and read command [read] this command starts a read operation. in addition, the start address of burst read is determined by the column address (see address pins table in pin function) and the bank select address (ba). after the read operation, the output buffer becomes high-z. read with auto-precharge [reada] this command automatically performs a pr echarge operation after a burst read with a burst length of 1, 2, 4 or 8. column address strobe and write command [writ] this command starts a write operation. when the burst write mode is sele cted, the column address (see address pins table in pin function) and the bank select address (ba) become the burst write start address. when the single write mode is selected, data is only written to the location specified by the column address (see address pins table in pin function) and the bank select address (ba). write with auto-precharge [writa] this command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a single write operation.
eds1616agta data sheet e0504e40 (ver. 4.0) 13 row address strobe and bank activate [act] this command activates the bank that is selected by ba and determines the row address (a0 to a10). (see bank select signal table) precharge selected bank [pre] this command starts precharge operation for the bank selected by ba. (see bank select signal table) [bank select signal table] ba bank 0 l bank 1 h remark: h: vih. l: vil. precharge all banks [pall] this command starts a precharge operation for all banks. refresh [ref/self] this command starts the refresh operati on. there are two types of refresh op eration, the one is auto-refresh, and the other is self-refresh. for details, refer to the cke truth table section. mode register set [mrs] the sdram has a mode register that defi nes how it operates. the mode regist er is specified by the address pins (a0 to a10 and ba) at the mode register set cycle. for details, refer to the mode regi ster configuration. after power on, the contents of the mode regi ster are undefined, exec ute the mode register set command to set up the mode register.
eds1616agta data sheet e0504e40 (ver. 4.0) 14 dqm truth table cke commands symbol n ? 1 n udqm ldqm upper byte write enable/output enable enbu h l lower byte write enable/output enable enbl h l upper byte write inhibit/output disable masku h h lower byte write inhibit/output disable maskl h h remark: h: vih. l: vil. : vih or vil write: l did is needed. read: l dod is needed. cke truth table cke current state function symbol n ? 1 n /cs /ras /cas /we address activating clock suspend mode entry h l any clock suspend mode l l clock suspend clock suspend mode exit l h idle cbr (auto) refresh command ref h h l l l h idle self refresh entry self h l l l l h self refresh self refresh exit l h l h h h l h h idle power down entry h l l h h h h l h power down power down exit l h h l h l h h h remark: h: vih. l: vil. : vih or vil
eds1616agta data sheet e0504e40 (ver. 4.0) 15 function truth table the following table shows the operations that are perfo rmed when each command is issued in each mode of the sdram. the following table assumes that cke is high. current state /cs /ras /cas /we address command operation precharge h desl enter idle after trp l h h h nop enter idle after trp l h h l bst illegal l h l h ba, ca, a10 read/reada illegal* 3 l h l l ba, ca, a10 writ/writa illegal* 3 l l h h ba, ra act illegal* 3 l l h l ba, a10 pre, pall nop* 5 l l l h ref, self illegal l l l l mode mrs illegal idle h desl nop l h h h nop nop l h h l bst illegal l h l h ba, ca, a10 read/reada illegal* 4 l h l l ba, ca, a10 writ/writa illegal* 4 l l h h ba, ra act bank and row active l l h l ba, a10 pre, pall nop l l l h ref, self refresh l l l l mode mrs mode register set* 8 row active h desl nop l h h h nop nop l h h l bst illegal l h l h ba, ca, a10 read/reada begin read* 6 l h l l ba, ca, a10 writ/writa begin write* 6 l l h h ba, ra act other bank active illegal on same bank* 2 l l h l ba, a10 pre, pall precharge* 7 l l l h ref, self illegal l l l l mode mrs illegal
eds1616agta data sheet e0504e40 (ver. 4.0) 16 current state /cs /ras /cas /we address command operation read h desl continue burst to end l h h h nop continue burst to end l h h l bst burst stop l h l h ba, ca, a10 read/reada continue burst read to /cas latency and new read l h l l ba, ca, a10 writ/writa term burst read/start write l l h h ba, ra act other bank active illegal on same bank* 2 l l h l ba, a10 pre, pall term burst read and precharge l l l h ref, self illegal l l l l mode mrs illegal read with auto- precharge h desl continue burst to end and precharge l h h h nop continue burst to end and precharge l h h l bst illegal l h l h ba, ca, a10 read/reada illegal* 3 l h l l ba, ca, a10 writ/writa illegal* 3 l l h h ba, ra act other bank active illegal on same bank* 2 l l h l ba, a10 pre, pall illegal* 3 l l l h ref, self illegal l l l l mode mrs illegal write h desl continue burst to end l h h h nop continue burst to end l h h l bst burst stop l h l h ba, ca, a10 read/reada term burst and new read l h l l ba, ca, a10 writ/writa term burst and new write l l h h ba, ra act other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall term burst write and precharge* 1 l l l h ref, self illegal l l l l mode mrs illegal
eds1616agta data sheet e0504e40 (ver. 4.0) 17 current state /cs /ras /cas /we address command operation write with auto- precharge h desl continue burst to end and precharge l h h h nop continue burst to end and precharge l h h l bst illegal l h l h ba, ca, a10 read/reada illegal* 3 l h l l ba, ca, a10 writ/writa illegal* 3 l l h h ba, ra act other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall illegal* 3 l l l h ref, self illegal l l l l mode mrs illegal refresh (auto-refresh) h desl enter idle after trc l h h h nop enter idle after trc l h h l bst illegal l h l h ba, ca, a10 read/reada illegal* 4 l h l l ba, ca, a10 writ/writa illegal* 4 l l h h ba, ra act illegal* 4 l l h l ba, a10 pre, pall illegal* 4 l l l h ref, self illegal l l l l mode mrs illegal mode register set h desl nop l h h h nop nop l h h l bst illegal l h l h ba, ca, a10 read/reada illegal* 4 l h l l ba, ca, a10 writ/writa illegal* 4 l l h h ba, ra act bank and row active* 9 l l h l ba, a10 pre, pall nop l l l h ref, self refresh* 9 l l l l mode mrs mode register set* 8 remark: h: vih. l: vil. : vih or vil notes: 1. an interval of tdpl is required betwe en the final valid data input and the precharge command. 2. if trrd is not satisfied, this operation is illegal. 3. illegal for same bank, except for another bank. 4. illegal for all banks. 5. nop for same bank, except for another bank. 6. illegal if trcd is not satisfied. 7. illegal if tras is not satisfied. 8. mrs command must be issued after dout finished, in case of dout remaining. 9. illegal if l mrd is not satisfied.
eds1616agta data sheet e0504e40 (ver. 4.0) 18 command truth table for cke cke current state n ? 1 n /cs /ras /cas /we address operation notes self refresh h invalid, clk (n ? 1) would exit self refresh l h h self refresh recovery l h l h h self refresh recovery l h l h l illegal l h l l illegal l l continue self refresh self refresh recovery h h h idle after t rc h h l h h idle after t rc h h l h l illegal h h l l illegal h l h illegal h l l h h illegal h l l h l illegal h l l l illegal power down h invalid, clk (n ? 1) would exit power down l h h exit power down l h l h h h exit power down l l continue power down mode all banks idle h h h refer to operations in function truth table h h l h refer to operations in function truth table h h l l h refer to operations in function truth table h h l l l h cbr (auto) refresh h h l l l l opcode refer to operations in function truth table h l h begin power down next cycle h l l h refer to operations in function truth table h l l l h refer to operations in function truth table h l l l l h self refresh 1 h l l l l l opcode refer to operations in function truth table l h exit power down next cycle l l power down 1 row active h refer to operations in function truth table l clock suspend 1 any state other than h h refer to operations in function truth table listed above h l begin clock suspend next cycle 2 l h exit clock suspend next cycle l l maintain clock suspend remark: h: vih. l: vil. : vih or vil notes: 1. self refresh can be entered only from the all ban ks idle state. power down can be entered only from all banks idle. clock suspend can be entered only from following states, row active, read, read with auto- precharge, write and writ e with auto precharge. 2. must be legal command as defined in function truth table.
eds1616agta data sheet e0504e40 (ver. 4.0) 19 clock suspend mode entry the sdram enters clock suspend mode from active mode by setting cke to low. if command is input in the clock suspend mode entry cycle, the command is valid. t he clock suspend mode changes depending on the current status (1 clock before) as shown below. active clock suspend this suspend mode ignores inputs after the next clock by internally maintaining the bank active status. read suspend and read with auto-precharge suspend the data being output is held (and continues to be output). write suspend and writ with auto-precharge suspend in this mode, external signals are not accept ed. however, the internal state is held. clock suspend during clock suspend mode, keep the cke to low. clock suspend mode exit the sdram exits from clock suspend mode by setti ng cke to high during the clock suspend state. idle in this state, all banks are not select ed, and completed precharge operation. auto-refresh command [ref] when this command is input from the idle state, the sdra m starts auto-refresh operation. (the auto-refresh is the same as the cbr refresh of conventional drams.) du ring the auto-refresh operation, refresh address and bank select address are generated inside the sdram. for ever y auto-refresh cycle, the in ternal address counter is updated. accordingly, 2048 times are required to refres h the entire memory. before executing the auto-refresh command, all the banks must be in the idle state. in addi tion, since the precharge for all banks is automatically performed after auto-refresh, no precharge co mmand is required after auto-refresh. self-refresh entry [self] when this command is input during the idle state, the sdram starts self-refresh operation. after the execution of this command, self-refresh continues while cke is low. si nce self-refresh is performed internally and automatically, external refresh operations are unnecessary. power down mode entry when this command is executed during the idle state, the sdram enters power down mode. in power down mode, power consumption is suppressed by cutting off the initial input circuit. self-refresh exit when this command is executed during self-refresh mode, t he sdram can exit from self-refresh mode. after exiting from self-refresh mode, the s dram enters the idle state. power down exit when this command is executed at the power down mode, the sdram can exit from power down mode. after exiting from power down mode, t he sdram enters the idle state.
eds1616agta data sheet e0504e40 (ver. 4.0) 20 simplified state diagram precharge write suspend read suspend row active idle idle power down auto refresh self refresh mode register set power on writea writea suspend reada reada suspend active clock suspend sr entry sr exit mrs refresh cke cke_ active write read write with ap read with ap power applied cke cke_ cke cke_ cke cke_ cke cke_ cke cke_ precharge ap read write write with ap read with read with ap write with ap precharge precharge precharge bst bst *1 read read write write automatic transition after completion of command. transition resulting from command input. note: 1. after the auto-refresh operation, precharge operation is performed automatically and enter the idle state.
eds1616agta data sheet e0504e40 (ver. 4.0) 21 mode register configuration mode register set the mode register is set by the input to the address pins (a0 to a10 and ba) during mode register set cycles. the mode register consists of five sections, each of which is assigned to address pins. ba, a8, a9, a10: (opcode): the sdram has two types of write modes. one is th e burst write mode, and the other is the single write mode. these bits specify write mode. ? burst read and burst write: burst write is performed for the specified burst length starting from the column address specified in the write cycle. ? burst read and single write: data is only written to t he column address specified during the write cycle, regardless of the burst length. a7: keep this bit low at the mode register set cycle. if this pin is high, the vender test mode is set. a6, a5, a4: (lmode): these pins specify the /cas latency. a3: (bt): a burst type is specified. a2, a1, a0: (bl): these pins specify the burst length. a2 a1 a0 burst length 00 0 1 00 1 2 01 0 4 01 1 8 11 1 bt=0 bt=1 10 0 r 11 0 r 1 2 4 8 r r r a3 0 sequential 1 interleave burst type a6 a5 a4 cas latency 00 0 r 00 1 r 01 0 2 01 1 3 1xx r a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 opcode 0 lmode bt bl 0 write mode 0 burst read and burst write 1 burst read and single write 0 10 1 r r f.p.: full page r is reserved (inhibit) x: 0 or 1 a10 x 0 ba ba a10 a9 a8 0 f.p. 0 mode register set
eds1616agta data sheet e0504e40 (ver. 4.0) 22 burst sequence a2 a1 a0 addressing(decimal) 00 0 00 1 01 0 01 1 11 1 interleave sequential 10 0 11 0 10 1 starting ad. 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 2, 3, 4, 5, 6, 7, 3, 4, 5, 6, 7, 4, 5, 6, 7, 5, 6, 7, 6, 7, 7, 0, 0, 1, 0, 1, 2, 0, 1, 2, 3, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 2, 3, 0, 1, 6, 7, 3, 2, 1, 0, 7, 4, 5, 6, 7, 5, 4, 7, 6, 7, 7, 6, 4, 5, 6, 5, 4, 0, 1, 2, 3, 6, 1, 0, 3, 2, 4, 5, 2, 3, 0, 1, 6, 5, 4, 3, 2, 1, 0, burst length = 8 a1 a0 addressing(decimal) 00 01 10 11 interleave sequential starting ad. 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0, burst length = 4 a0 addressing(decimal) 0 1 interleave sequential starting ad. 0, 1, 1, 0, 0, 1, 1, 0, burst length = 2 burst sequence full page burst is available only for sequential addressing. the addressing sequence is started from the column address that is asserted by read/write command. and the address is increased one by one. it is back to the address 0 when the address reaches at th e end of address 255. ?full page burst? stops the burst read/write with burst stop command.
eds1616agta data sheet e0504e40 (ver. 4.0) 23 power-up sequence power-up sequence the sdram should be goes on the following sequence with power up. the clk, cke, /cs, dqm and dq pi ns keep low till power stabilizes. the clk pin is stabilized within 100 s after power st abilizes before the following initialization sequence. the cke and dqm is driven to high between powe r stabilizes and the initialization sequence. this sdram has vdd clamp diodes for clk, cke, addre ss, /ras, /cas, /we, /cs, dqm and dq pins. if these pins go high before power up, the large current fl ows from these pins to vdd through the diodes. initialization sequence when 200 s or more has past after the above power- up sequence, all banks must be precharged using the precharge command (pall). after trp delay, set 8 or more auto refresh commands (ref). set the mode register set command (mrs) to initialize the mode register. we recommend that by keeping dqm and cke to high, the output buffer becomes high-z during initialization sequence, to avoid dq bus contention on memory system formed with a number of device. vdd, vddq power up sequence initialization sequence 100 s 0 v low low low cke, dqm clk /cs, dq 200 s power stabilize power-up sequence and initialization sequence
eds1616agta data sheet e0504e40 (ver. 4.0) 24 operation of the sdram read/write operations bank active before executing a read or write operat ion, the corresponding bank and the row address must be activated by the bank active (act) command. an interval of trcd is required between the bank ac tive command input and the following read/wri te command input. read operation a read operation starts when a read command is input. output buffer becomes low-z in the (/cas latency - 1) cycle after read command set. the sdram can perform a burst read operation. the burst length can be set to 1, 2, 4, 8 and full page (ful l page: sequential only). the start address for a burst read is specified by the column address and the bank select addr ess at the read command set cycle. in a read operation, data output starts after the number of cl ocks specified by the /cas latency. t he /cas latency can be set to 2 or 3. when the burst length is 1, 2, 4, 8 and full page (full page: sequential on ly), the dout buffer automatically becomes high-z at the next clock after the succe ssive burst-length data has been output. the /cas latency and burst length must be specified at the mode register. read clk command dq act row column address cl = 2 cl = 3 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 trcd cl = /cas latency burst length = 4 /cas latency read clk command dq act row column out 0 out 6 out 7 address out 0 out 1 out 4 out 5 out 0 out 1 out 2 out 3 bl = 1 out 0 out 1 out 2 out 3 bl = 2 bl = 4 bl = 8 trcd bl : burst length /cas latency = 2 burst length
eds1616agta data sheet e0504e40 (ver. 4.0) 25 write operation burst write or single write mode is select ed by the opcode of the mode register. 1. burst write: a burst write operation is enabled by setting opcode (a9, a8) to (0, 0). a burst write starts in the same clock as a write command set. (the latency of data input is 0 clock.) the burst length can be set to 1, 2, 4 , 8 and full page (full page: sequential only),, like burst r ead operations. the write star t address is specified by the column address and the bank select address at the write command set cycle. writ clk command dq act row column in 0 in 6 in 7 address in 1 in 4 in 5 in 3 bl = 1 bl = 2 bl = 4 bl = 8 trcd in 0 in 0 in 0 in 1 in 1 in 2 in 2 in 3 cl = 2, 3 burst write 2. single write: a single write op eration is enabled by setting opcode (a9, a8) to (1, 0). in a single write operation, data is only written to the column address and the bank select address specified by the write command set cycle without regard to the burst length setting. (the latency of data input is 0 clock). writ clk command dq act row column in 0 address trcd single write
eds1616agta data sheet e0504e40 (ver. 4.0) 26 auto precharge read with auto-precharge in this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. the command executed for the same bank after the execution of this command must be the bank active (a ct) command. in addition, an interval defined by l apr is required before executio n of the next command. [clock cycle time] /cas latency precharge start cycle 3 2 cycle before the final data is output 2 1 cycle before the final data is output clk l apr l ras l apr cl=2 command cl=3 command dq dq note: internal auto-precharge starts at the timing indicated by " ". and an interval of tras ( l ras) is required between previous active (act) command and internal precharge " ". act reada act out3 out2 out1 out0 l ras act reada act out3 out2 out1 out0 burst read (bl = 4) write with auto-precharge in this operation, since precharge is automatically performe d after completing a burst write or single write operation, a precharge command need not be executed after each write operation. the command executed for the same bank after the execution of this command must be the bank active (act) command. in addition, an interval of l dal is required between the final valid data input and input of next command. clk command dq l dal l ras act writa in0 in1 in2 in3 act note: internal auto-precharge starts at the timing indicated by " ". and an interval of tras ( l ras) is required between previous active (act) command and internal precharge " ". burst write (bl = 4)
eds1616agta data sheet e0504e40 (ver. 4.0) 27 clk command dq l dal l ras act writa in act note: internal auto-precharge starts at the timing indicated by " ". and an interval of tras ( l ras) is required between previous active (act) command and internal precharge " ". single write
eds1616agta data sheet e0504e40 (ver. 4.0) 28 burst stop command during a read cycle, when the burst stop command is issued, the burst read data ar e terminated and the data bus goes to high-z after the /cas lat ency from the burst stop command. clk command dq (cl = 2) dq (cl = 3) read bst out out out out out out high-z high-z burst stop at read during a write cycle, when the burst stop command is issued, the burst writ e data are terminated and data bus goes to high-z at the same clock with the burst stop command. clk command dq in in in bst write in high-z burst stop at write
eds1616agta data sheet e0504e40 (ver. 4.0) 29 command intervals read command to read command interval 1. same bank, same row address: when another read command is executed at the same row address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. clk command dq out b3 address out b1 out b2 bs act row column a read read column b out a0 out b0 bank0 active column =a read column =b read column =a dout column =b dout cl = 3 bl = 4 bank 0 read to read command interval (same row address in same bank) 2. same bank, different row address: when the ro w address changes on same bank, consecutive read commands cannot be executed; it is necessary to se parate the two read commands with a precharge command and a bank active command. 3. different bank: when the bank changes, the second read can be performed after an interval of no less than 1 clock, provided that the othe r bank is in the bank active state. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. clk command dq out b3 address out b1 out b2 bs act row 0 row 1 act read column a out a0 out b0 bank0 active bank1 active bank0 read bank1 read read column b bank0 dout bank1 dout cl = 3 bl = 4 read to read command interval (different bank)
eds1616agta data sheet e0504e40 (ver. 4.0) 30 write command to write command interval 1. same bank, same row address: when another write command is execut ed at the same row address of the same bank as the preceding write command, the second wr ite can be performed after an interval of no less than 1 clock. in the case of burst writes , the second write command has priority. clk command dq in b3 address in b1 in b2 bs act row column a writ writ column b in a0 in b0 bank0 active column =a write column =b write burst write mode bl = 4 bank 0 write to write command interval (same row address in same bank) 2. same bank, different row address: when the row address changes, co nsecutive write commands cannot be executed; it is necessary to separ ate the two write commands with a precharge command and a bank active command. 3. different bank: when the bank changes, the second writ e can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. in the case of burst write, the second write command has priority. clk command dq in b3 address in b1 in b2 bs act row 0 row 1 act writ column a in a0 in b0 bank0 active bank1 active bank0 write bank1 write writ column b burst write mode bl = 4 write to write command interval (different bank)
eds1616agta data sheet e0504e40 (ver. 4.0) 31 read command to write command interval 1. same bank, same row address: when the write comma nd is executed at the same row address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. however, udqm and ldqm must be set high so that the output buffer becom es high-z before data input. clk command dq (output) in b2 in b3 read writ in b0 in b1 high-z dq (input) cl=2 cl=3 udqm ldqm bl = 4 burst write read to write command interval (1) clk command dq read writ cl=2 cl=3 udqm ldqm 2 clock out out out out out in in in in in in in in read to write command interval (2) 2. same bank, different row address: when the row address changes, co nsecutive write commands cannot be executed; it is necessary to separate the two co mmands with a precharge command and a bank active command. 3. different bank: when the bank changes, the write co mmand can be performed after an interval of no less than 1 cycle, provided that the ot her bank is in the bank active state. however, udqm and ldqm must be set high so that the output buffer becom es high-z before data input.
eds1616agta data sheet e0504e40 (ver. 4.0) 32 write command to read command interval: 1. same bank, same row address: when the read comm and is executed at the same row address of the same bank as the preceding write command, the read command c an be performed after an interval of no less than 1 clock. however, in the case of a burst write, data will continue to be written until one clock before the read command is executed. clk command dq (input) writ read in a0 out b1 out b2 out b3 out b0 dq (output) column = a write column = b read column = b dout /cas latency udqm ldqm burst write mode cl = 2 bl = 4 bank 0 write to read command interval (1) clk command dq (input) writ read in a0 out b1 out b2 out b3 out b0 dq (output) column = a write column = b read column = b dout /cas latency in a1 udqm ldqm burst write mode cl = 2 bl = 4 bank 0 write to read command interval (2) 2. same bank, different row address: when the row address changes, consecutive read commands cannot be executed; it is necessary to separate the two co mmands with a precharge command and a bank active command. 3. different bank: when the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that t he other bank is in the bank active state. however, in the case of a burst write, data will continue to be written until one clock before the read comm and is executed (as in the case of the same bank and the same address).
eds1616agta data sheet e0504e40 (ver. 4.0) 33 read with auto precharge to read command interval 1. different bank: when some banks are in the active stat e, the second read command (another bank) is executed. even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is valid. the internal auto-precharge of one bank starts at the next cl ock of the second command. clk command bs dq reada read out a0 out a1 out b0 out b1 cl= 3 bl = 4 bank0 read a bank1 read note: internal auto-precharge starts at the timing indicated by " ". read with auto precharge to read command interval (different bank) 2. same bank: the consecutive read command (the same bank) is illegal. write with auto precharge to write command interval 1. different bank: when some banks are in the active stat e, the second write command (another bank) is executed. in the case of burst writes, the se cond write command has priority. the internal auto-precharge of one bank starts 2 clocks later from the second command. clk command bs dq writa writ in b1 in b2 in b3 in a0 in a1 in b0 bl= 4 bank0 write a bank1 write note: internal auto-precharge starts at the timing indicated by " ". write with auto precharge to writ e command interval (different bank) 2. same bank: the consecutive writ e command (the same bank) is illegal.
eds1616agta data sheet e0504e40 (ver. 4.0) 34 read with auto precharge to write command interval 1. different bank: when some banks are in the active stat e, the second write command (another bank) is executed. however, udqm and ldqm must be set high so that t he output buffer becomes high-z before data input. the internal auto-precharge of one bank starts at the next clock of the second command. clk command bs dq (output) dq (input) cl = 2 cl = 3 reada writ in b0 in b1 in b2 in b3 bl = 4 bank0 reada bank1 write note: internal auto-precharge starts at the timing indicated by " ". udqm ldqm high-z read with auto precharge to write command interval (different bank) 2. same bank: the consecutive write command from read wi th auto precharge (the same bank) is illegal. it is necessary to separate the two commands with a bank active command. write with auto precharge to read command interval 1. different bank: when some banks are in the active stat e, the second read command (another bank) is executed. however, in case of a burst write, data will continue to be written unt il one clock before the read command is executed. the internal auto-precharge of one bank st arts at 2 clocks later from the second command. clk command bs dq (output) dq (input) writa read out b0 out b1 out b2 out b3 cl = 3 bl = 4 bank0 writea bank1 read note: internal auto-precharge starts at the timing indicated by " ". udqm ldqm in a0 write with auto precharge to read command interval (different bank) 2. same bank: the consecutive read command from write wi th auto precharge (the same bank) is illegal. it is necessary to separate the two commands with a bank active command.
eds1616agta data sheet e0504e40 (ver. 4.0) 35 read command to precharge command interval (same bank) when the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. howeve r, since the output buffer then becomes high-z after the clocks defined by l hzp, there is a case of interr uption to burst read dat a output will be interrupt ed, if the precharge command is input during burst read. to read all data by burst read, the clocks defined by l ep must be assured as an interval from the final data output to precharge command execution. clk command dq read pre/pall out a0 out a1 out a2 out a3 cl=2 l ep = -1 cycle read to precharge command interval (same bank): to output all data (cl = 2, bl = 4) clk command dq read pre/pall out a0 out a1 out a2 out a3 cl=3 l ep = -2 cycle read to precharge command interval (same bank): to output all data (cl = 3, bl = 4) clk command dq read pre/pall out a0 high-z l hzp = 2 read to precharge command interval (same bank): to stop output data (cl = 2, bl = 1, 2, 4, 8) clk command dq read pre/pall out a0 l hzp =3 high-z read to precharge command interval (same bank): to stop output data (cl = 3, bl = 1, 2, 4, 8)
eds1616agta data sheet e0504e40 (ver. 4.0) 36 write command to precharge command interval (same bank) when the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. however, if the burst write operation is unfinis hed, the input data must be masked by means of udqm and ldqm for assurance of the clock defined by tdpl. clk in a0 in a1 in a2 command dq writ pre/pall udqm ldqm tdpl write to precharge command interval (same bank) (bl = 4 (to stop write operation)) clk in a0 in a1 in a2 command dq writ pre/pall in a3 udqm ldqm tdpl write to precharge command interval ( same bank) (bl = 4 (to write all data))
eds1616agta data sheet e0504e40 (ver. 4.0) 37 bank active command interval 1. same bank: the interval between the two bank active commands must be no less than trc. 2. in the case of different bank active commands: t he interval between the two bank active commands must be no less than trrd. clk command address bs bank 0 active act row act row bank 0 active trc bank active to bank active for same bank clk command address bs bank 0 active bank 1 active act row:0 act row:1 trrd bank active to bank active for different bank mode register set to bank active command interval the interval between setting the mode register and executing a bank active command must be no less than l mrd. clk command address mode register set bank active mrs l mrd act bs & row opcode mode register set to bank active command interval
eds1616agta data sheet e0504e40 (ver. 4.0) 38 dqm control the udqm and ldqm mask the upper and lower bytes of t he dq data, respectively. the timing of udqm and ldqm is different during reading and writing. reading when data is read, the output buffer can be controlled by udqm and ldqm. by setting udqm and ldqm to low, the output buffer becomes low-z, enabling data output. by setting udqm and ldqm to high, the output buffer becomes high-z, and the corresponding data is not output. however, internal reading operations continue. the latency of udqm and ldqm during reading is 2 clocks. writing input data can be masked by udqm and ldqm. by setting dqm to low, data can be written. in addition, when udqm and ldqm are set to high, the corresponding data is not written, and the previous data is held. the latency of udqm and ldqm during writing is 0 clock. clk dq out 0 out 1 l dod = 2 latency out 3 udqm ldqm high-z reading clk dq in 0 in 1 l did = 0 latency in 3 udqm ldqm writing
eds1616agta data sheet e0504e40 (ver. 4.0) 39 refresh auto-refresh all the banks must be precharged before executing an auto-refresh command. since the auto-refresh command updates the internal counter every time it is executed and determines the banks and the row addresses to be refreshed, external address specificat ion is not required. the refresh cycles are required to refresh all the row addresses within tref (max.). the output buffer becomes high-z after auto-refresh start. in addition, since a precharge has been completed by an internal operation a fter the auto-refresh, an additional precharge operation by the precharge command is not required. self-refresh after executing a self-refresh command, the self-refresh oper ation continues while cke is held low. during self- refresh operation, all row addr esses are refreshed by the internal refresh timer. a self-refresh is terminated by a self-refresh exit command. before and after self-refresh m ode, execute auto-refresh to all refresh addresses in or within tref (max.) period on the condition 1 and 2 below. 1. enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. 2. start burst refresh or distributed re fresh at equal interval to all refresh addresses within time as below*after exiting from self-refresh mode. note: tref (max.) / refresh cycles. others power-down mode the sdram enters power-down mode when cke goes low in the idle state. in power down mode, power consumption is suppressed by deactivating the input initia l circuit. power down mode continues while cke is held low. in addition, by setting cke to high, the sdram exits from the power down mode, and command input is enabled from the next clock. in this mode, internal refresh is not performed. clock suspend mode by driving cke to low during a bank active or read/write operation, the sdram enters clock suspend mode. during clock suspend mode, external input signals are ignored and the internal state is maintained. when cke is driven high, the sdram terminates clock suspend mode, and command input is enabled from the next clock. for details, refer to the "cke truth table".
eds1616agta data sheet e0504e40 (ver. 4.0) 40 timing waveforms read cycle bank 0 active bank 0 read bank 0 precharge clk cke /cs tras trcd thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi /ras /cas /we bs a10 address dqm dq (input) dq (output) thi tsi tch t tck t ac t ac cl t ac t oh t oh t oh t oh t rp trc /cas latency = 2 burst length = 4 bank 0 access = vih or vil = voh or vol thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi t t lz vih t hz ac
eds1616agta data sheet e0504e40 (ver. 4.0) 41 write cycle clk cke /cs tras trcd /ras /cas /we bs a10 address dq (input) dq (output) tch t tck thi thi cl thi thi tsi tsi tsi tsi trp trc tdpl bank 0 write thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi thi tsi tsi bank 0 active bank 0 precharge vih cl = 2 bl = 4 bank 0 access = vih or vil udqm ldqm thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi thi tsi mode register set cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke /cs /ras /cas /we bs address udqm ldqm dq (input) dq (output) high-z b b+3 b? b?+1 b?+2 b?+3 l mrd valid c: b? code l rcd l rp precharge if needed mode register set bank 1 active bank 1 read r: b c: b output mask vih l rcd = 3 /cas latency = 3 burst length = 4 = vih or vil
eds1616agta data sheet e0504e40 (ver. 4.0) 42 read cycle/write cycle 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 r:a c:a r:b c:b c:b' c:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 cke /ras /cs /cas /we address udqm, ldqm udqm, ldqm dq (output) dq (input) clk bs r:a c:a r:b c:b c:b' c:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 bank 0 active bank 0 read bank 1 active bank 1 read bank 1 read bank 1 read bank 0 precharge bank 1 precharge bank 0 active bank 0 write bank 1 active bank 1 write bank 1 write bank 1 write bank 0 precharge bank 1 precharge cke /ras /cs /cas /we address dq (input) dq (output) bs high-z high-z vih read cycle /ras-/cas delay = 3 /cas latency = 3 burst length = 4 = vih or vil write cycle /ras-/cas delay = 3 /cas latency = 3 burst length = 4 = vih or vil vih read/single write cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 r:a c:a r:b c:a' r:a c:a c:a a a a a bank 0 active bank 0 read bank 1 active bank 0 write bank 0 precharge bank 1 precharge bank 0 active bank 0 read bank 0 write bank 0 precharge r:b bank 1 active c:a bank 0 read a a+1 a+2 a+3 bank 0 write bank 0 write cke /ras /cs /cas /we address udqm, ldqm dq (input) dq (output) clk bs cke /ras /cs /cas /we address udqm, ldqm bs c:b bc a+1 a+3 a+1 a+2 a+3 c:c v ih v ih read/single write /ras-/cas delay = 3 /cas latency = 3 burst length = 4 = vih or vil dq (input) dq (output)
eds1616agta data sheet e0504e40 (ver. 4.0) 43 read/burst write cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 r:a c:a r:b c:a' r:a c:a c:a a a+1 a+2 a+3 a+1 a a+1 a+2 a+3 bank 0 active bank 0 read bank 0 write bank 0 precharge r:b bank 1 active cke /ras /cs /cas /we address udqm, ldqm clk bs cke /ras /cs /cas /we address udqm, ldqm bs a+1 a+2 a+3 a a+3 a bank 0 active bank 0 read bank 1 active clock suspend bank 0 write bank 0 precharge bank 1 precharge vi h read/burst write /ras-/cas delay = 3 /cas latency = 3 burst length = 4 = vih or vil dq (input) dq (output) dq (input) dq (output) auto refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 clk cke /cs /cas /we bs address udqm ldqm dq (input) dq (output) high-z rp precharge if needed auto refresh active bank 0 t rc t rc t auto refresh read bank 0 r:a c:a a10=1 /ras a a+1 vih refresh cycle and read cycle /ras-/cas delay = 2 /cas latency = 2 burst length = 4 = vih or vil
eds1616agta data sheet e0504e40 (ver. 4.0) 44 self refresh cycle clk cke /cs /ras /cas /we bs address udqm ldqm dq (input) dq (output) precharge command if needed self refresh entry command auto refresh self refresh exit ignore command or no operation cke low a10=1 rc t rp t self refresh cycle /ras-/cas delay = 3 cl = 3 bl = 4 = vih or vil high-z next clock enable rc t next clock enable lsrex self refresh entry command clock suspend mode 0123 4 5 6 7 8 9 1011121314151617181920 r:a c:a r:b a a+1 a+2 a+3 b b+1 b+2 r:a c:a r:b c:b a a+1 a+2 b b+1 b+2 b+3 c:b bank0 active active clock suspend start active clock supend end bank0 read bank1 active read suspend start read suspend end bank0 precharge bank1 read earliest bank1 precharge bank0 write bank0 active active clock suspend start active clock suspend end bank1 active write suspend start write suspend end bank1 write bank0 precharge earliest bank1 precharge b+3 cke /ras /cs /cas /we address udqm, ldqm clk bs cke /ras /cs /cas /we address udqm, ldqm bs a+3 high-z high-z thi tsi tsi read cycle /ras-/cas delay = 2 /cas latency = 2 burst length = 4 = vih or vil write cycle /ras-/cas delay = 2 /cas latency = 2 burst length = 4 = vih or vil dq (output) dq (input) dq (output) dq (input)
eds1616agta data sheet e0504e40 (ver. 4.0) 45 power down mode clk cke /cs /ras /cas /we bs address udqm ldqm dq (input) dq (output) precharge command if needed power down entry active bank 0 power down mode exit cke low r: a a10=1 rp t high-z power down cycle /ras-/cas delay = 3 /cas latency = 3 burst length = 4 = vih or vil initialization sequence 78910 52 53 54 48 49 50 51 auto refresh bank active if needed rc t rc t auto refresh valid 0 123456 clk cke /cs /ras /cas /we address udqm ldqm dq valid l mrd trp all banks precharge mode register set v ih vih 55 high-z code
eds1616agta data sheet e0504e40 (ver. 4.0) 46 package drawing 50-pin plastic tsop (ll) solder plating: lead free (sn-bi) unit: mm eca-ts2-0139-01 0.13 ms s s a a b b 0.10 0.80 10.16 50 26 125 20.95 0.15* 1 1.0 0.05 1.2 max. 11.76 0.20 0.10 0.05 0 to 8 0.12 to 0.21 0.30 to 0.45 0.50 0.10 0.80 nom 0.25 pin#1 id note: 1. this dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 0.875
eds1616agta data sheet e0504e40 (ver. 4.0) 47 recommended soldering conditions please consult with our sales offices for soldering conditions of the eds1616agta. type of surface mount device eds1616agta: 50-pin plastic tsop (ll) < lead free (sn-bi) >
eds1616agta data sheet e0504e40 (ver. 4.0) 48 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
eds1616agta data sheet e0504e40 (ver. 4.0) 49 m01e0107 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

▲Up To Search▲

Price & Availability of EDS1616AGTA-75-E

	To Download EDS1616AGTA-75-E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .